Items where Author is "Földesy, Péter"

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Group by: Date | Item Type | No Grouping
Number of items: 64.
DateAuthor/TitleDocument Type
2016Németh, Máté and Zarándy, Ákos and Földesy, Péter
Dual-pixel CMOS APS Architecture for Intra-frame Speed Measurement
Book Section
2016Németh, Máté and Zarándy, Ákos and Földesy, Péter
Pixel-level APS Sensor Integration and Sensitivity Scaling for Vision Based Speed Measurement
Article
2015Gergelyi, Domonkos and Földesy, Péter and Zarándy, Ákos
Scalable, Low-Noise Architecture for Integrated Terahertz Imagers
Article
2013Földesy, Péter
Current steering detection scheme of three terminal antenna-coupled terahertz field effect transistor detectors
ISI Article
2013Földesy, Péter
Terahertz responsivity of field-effect transistors under arbitrary biasing conditions
ISI Article
2013Carmona-Galán, Ricardo and Zarándy, Ákos and Rekeczky, Csaba and Földesy, Péter and Pérez, A and Matas, C and Berni, J and Cembrano, G and Verdú, B and Kárász, Zoltán and Cambre, M and Sánchez, V and Roska, Tamás and Vázquez, A
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
ISI Article
2012Földesy, Péter
Antenna csatolt érzékelők kvadratúra interferogramjának rögzítésére szolgáló elrendezés és eljárás
Patent
2012Földesy, Péter
Characterization of silicon field effect transistor sub-THz detectors for imaging systems
Conference or Workshop Item
2012Földesy, Péter
Eszköz és eljárás interferencia-mintázat érzékelésére
Patent
2012Földesy, Péter and Zarándy, Ákos
Integrated CMOS sub-THz imager array
Conference or Workshop Item
2012Földesy, Péter and Fekete, Zoltán and Párdy, T and Gergelyi, Domonkos
Terahertz Spatial Light Modulator with Digital Microfluidic Array
Article
2012Földesy, Péter
Terahertz single-shot quadrature phase-shifting interferometry
ISI Article
2012Földesy, Péter and Gergelyi, Domonkos and Füzy, Cs and Károlyi, G
Test and configuration architecture of a sub-THz CMOS detector array
Conference or Workshop Item
2011Zarándy, Ákos and Rekeczky, Csaba and Földesy, Péter and Carmona-Galán, Ricardo and Linán-Cembrano, Gustavo and Sós, Gergely and Rodríguez-Vázquez, Angel and Roska, Tamás
VISCUBE: a multi-layer vision chip
Book Section
2011Zarándy, Ákos and Rekeczky, Csaba and Földesy, Péter and Galán, R and Cembrano, G and Sós, G and Vázquez, A and Roska, Tamás
VISCUBE: a multi-layer vision chip. In: Focal-plane sensor-processor chips
Book Section
2010-02-03Gergelyi, Domonkos and Földesy, Péter
Digital micromirror device (DMD) projector based test bench for vision chips
Conference or Workshop Item
2010-02-03Földesy, Péter and Carmona-Galan, R. and Zarándy, Ákos and Rekeczky, Cs. and Rodríguez-Vázquez, A. and Roska, Tamás
Digital processor array implementation aspects of a 3D multi-layer vision architecture
Conference or Workshop Item
2010-02-03Zarándy, Ákos and Fekete, D. and Földesy, Péter and Soós, G. and Rekeczky, Cs.
Displacement calculation algorithm on a heterogeneous multi-layer cellular sensor processor array
Conference or Workshop Item
2010Rodríguez-Vázquez, A. and Carmona, R. and Domínguez Matas, C. and Suárez-Cambre, M. and Brea, V. and Pozas, F. and Linán, G. and Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba
A 3-D chip architecture for optical sensing and concurrent processing
Conference or Workshop Item
2010Zarándy, Ákos and Földesy, Péter and Carmona, R. and Rekeczky, Cs. and Bean, J. A. and Porod, W.
Cellular multi-core processor carrier chip for nanoantenna integration and experiments
Book Section
2009-08-23Földesy, Péter and Carmona-Galan, R. and Zarándy, Ákos and Rekeczky, Cs. and Rodríguez-Vázquez, A. and Roska, Tamás
3D multi-layer vision architecture for surveillance and reconnaissance applications
Conference or Workshop Item
2008Zarándy, Ákos and Rekeczky, Csaba and Földesy, Péter
Analysis of 2D operators on topographic and non-topographic processor architectures
Conference or Workshop Item
2008Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba
Clusterable cellular visual microprocessor
Conference or Workshop Item
2008Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba
Configurable 3D-integrated focal-plane sensor-processor array architecture
ISI Article
2007Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba and Roska, Tamás
3D integrated scalable focal-plane processor array
Conference or Workshop Item
2007Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba and Roska, Tamás
High performance processor array for image processing
Conference or Workshop Item
2006Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba and Roska, Tamás
Digital implementation of the cellular sensor-computers
ISI Article
2005Zarándy, Ákos and Földesy, Péter and Roska, Tamás
Per-pixel integration time controlled image sensor
Conference or Workshop Item
2005Zarándy, Ákos and Földesy, Péter and Szolgay, Péter and Tőkés, Szabolcs and Rekeczky, Csaba and Roska, Tamás
Various implementations of topographic, sensory, cellular wave computers
Conference or Workshop Item
2004Földesy, Péter
Trends in design of massively parallel coprocessors implemented in digital ASICs
Conference or Workshop Item
2003Rekeczky, Csaba and Petrás, István and Szatmári, István and Földesy, Péter
Active wave computing on silicon: chip experiments
Conference or Workshop Item
2003Cserey, György and Rekeczky, Csaba and Földesy, Péter
PDE-based histogram modification with embedded morphological processing of the level-sets
Article
2003Zarándy, Ákos and Rekeczky, Csaba and Földesy, Péter and Szatmári, István
The new framework of applications: the Aladdin system
Article
2002Rekeczky, Csaba and Szatmári, István and Földesy, Péter and Roska, Tamás
Analogic cellular PDE machines
Conference or Workshop Item
2002Szatmári, István and Földesy, Péter and Rekeczky, Csaba and Zarándy, Ákos
Image processing library for the ALADDIN visual computer
Conference or Workshop Item
2002Földesy, Péter and Szatmári, István and Zarándy, Ákos
Moving object traking on panoramic images
Conference or Workshop Item
2002Cserey, György and Rekeczky, Csaba and Földesy, Péter
PDE based histogram modification with embedded morphological processing of the level-sets
Conference or Workshop Item
2002Földesy, Péter
Statistical error modeling of CNN-UM architectures: The binary case
Conference or Workshop Item
2002Földesy, Péter and Rodríguez-Vázquez, Á.
A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips
Article
2001Földesy, Péter and Rodíguez-Vázquez, A.
Behavioral modeling concept and practice of CNN-UM VLSI implementations
Conference or Workshop Item
2001Rekeczky, Csaba and Szatmári, István and Földesy, Péter
Computing on silicon with trigger-waves: experiments on CNN-UM chips
Conference or Workshop Item
2000Zarándy, Ákos and Espejo, S. and Földesy, Péter and Kék, László and Linán, G. and Rekeczky, Csaba and Rodriguez-Vázquez, A. and Roska, Tamás and Szatmári, István and Szirányi, Tamás and Szolgay, Péter
CNN technology in action
Conference or Workshop Item
2000Földesy, Péter
CNN-UM architektúrák hibamodellezése és alkalmazhatóságuk kiterjesztése - modellezés, analízis és műveleti szintézis
Thesis
2000Linán, G. and Földesy, Péter and Rodríguez-Vázquez, A. and Espejo, S. and Dominiguez-Castro, R.
Implementation of non-linear templates using a decomposition technique by a 0.5mm CMOS CNN universal chip
Conference or Workshop Item
2000Földesy, Péter and Linan, G. and Rodriguez-Vázquez, A. and Espejo, S. and Dominguez-Castro, R.
Object oriented image segmentation on the CNNUC3 chip
Conference or Workshop Item
2000Linán, G. and Földesy, Péter and Rodríguez-Vázquez, A. and Espejo, S. and Dominguez-Castro, R.
Realization of non-linear templates using the CNNUC3 prototype
Conference or Workshop Item
2000Földesy, Péter and Linán, G. and Rodriguez-Vázquez, A. and Espejo, S. and Dominguez-Castro, R.
Sructure reconfigurability of the CNNUC3 for robust template operation
Conference or Workshop Item
2000Szatmári, István and Zarándy, Ákos and Földesy, Péter and Kék, László
An analogic CNN engine board with the 64x64 analog I/O CNN-UM chip
Conference or Workshop Item
2000Zarándy, Ákos and Roska, Tamás and Szolgay, Péter and Földesy, Péter and Zöld, S.
A development system for prototyping and interfacing CNN chips and for analogic algorithm design
Book Section
1999Zarándy, Ákos and Roska, Tamás and Szolgay, Péter and Zöld, S. and Földesy, Péter and Petrás, István
CNN chip prototyping and development systems
Conference or Workshop Item
1999Földesy, Péter and Kék, László and Zarándy, Ákos and Roska, Tamás and Bártfai, Gusztáv
Fault-tolerant design of analogic CNN templates and algorithms - Part I: The binary output case
Article
1999Szolgay, Péter and Zarándy, Ákos and Zöld, S. and Roska, Tamás and Földesy, Péter and Kék, László and Kozek, T. and László, K. and Petrás, István and Rekeczky, Csaba and Szatmári, István and Bálya, Dávid
The computational infrastructure for cellular visual microprocessors
Conference or Workshop Item
1999Roska, Tamás and Zarándy, Ákos and Zöld, S. and Földesy, Péter and Szolgay, Péter
The computational infrastructure of analogic CNN computing - Part I: The CNN-UM chip prototyping system
Article
1998Földesy, Péter and Kék, László and Roska, Tamás and Zarándy, Ákos and Bártfai, Gusztáv
Fault tolerant CNN template design and optimatization based on chip measurements
Conference or Workshop Item
1998Földesy, Péter and Kék, László and Zarándy, Ákos and Roska, Tamás and Bártfai, Gusztáv
Fault tolerant design of analogic CNN templates and algorithms. Part I: The binary output case.(Research report of the Analogical and Neural Computing Laboratory, DNS-3-1998.)
Book
1998Tömördi, K. and Földesy, Péter and Szolgay, Péter
On the chip implementation of analogic algorithms for optical detection of some layout errors of printed circuit boards
Conference or Workshop Item
1997Domínguez-Castro, R. and Espejo, S. and Rodríguez-Vázquez, A. and Carmona, RA and Földesy, Péter and Zarándy, Ákos and Szolgay, Péter and Szirányi, Tamás and Roska, Tamás
0.8-?m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
Article
1997Földesy, Péter and Szolgay, Péter
A CNN engine board
Conference or Workshop Item
1997Zarándy, Ákos and Cruz, M. and Szolgay, Péter and Földesy, Péter and Chua, LO and Roska, Tamás
Functional measurements of the first analog input/output CNN universal chip. (Research report of the Analogical and Neural Computing Laboratory, DNS-4-1997.)
Book
1996Tóth, Gábor András and Földesy, Péter and Roska, Tamás
Distance preserving 1D turing-pattern models via CNN, implementing of complex-valued CNN, and solving a simple inverse pattern problem (detection).( Research report of the Analogical and Neural Computing Laboratory, DNS-3-1996.)
Book
1996Tóth, Gábor András and Földesy, Péter and Roska, Tamás
Distance preserving 1D turing-wave models via CNN, implementation of complex-valued CNN and solving a simple inverse pattern problem (detection)
Conference or Workshop Item
1996Földesy, Péter and Zarándy, Ákos and Szolgay, Péter and Szirányi, Tamás
Real-life application case studies using CMOS 0.8 mm CNN universal chip: analogic algorithm for motion detection and texture segmentation
Conference or Workshop Item
1996Szolgay, Péter and Földesy, Péter and Gubai, GY and Kukoda, G.
The first steps toward the application of the CNN chips
Conference or Workshop Item
1995Földesy, Péter and Szolgay, Péter
A CNN platform to a discrete-time cellular neural network universal machine chip. (Research report of the Analogical and Neural Computing Laboratory DNS-12-1995.)
Book
This list was generated on Mon Oct 14 03:05:02 2019 CEST.